Research Team Publications
Dalton: An Associative Memory Approach to Parallel Logic Event-driven Simulation; Proc of the Annual European Conference on Computer Systems and Software Engineering. The Hague, May 1992, IEEE Comp Soc Press, pp. 341–346.
Dalton: A Special Purpose Hybrid SIMD Processor for Logic Event Simulation; Proc of the 7th Euromicro Workshop on Parallel and Distributed Processing. PDP’99. Funchal, Madeira, Portugal, Feb 1999.
Dalton: A New timing Mechanism Architecture for Discrete Logic Event Simulation; Proc Int'l Conf on Parallel and Distributed Processing Techniques and Applications ; PDPTA '99. Las Vegas, Nevada, USA, June 1999. CSREA press.
Dalton: The Speedup Performance of An Associative Memory Based Logic Simulator; Proc 5th Int'l Conf on Parallel Computation Technologies. PaCT-99, Russian Academy of Sciences/State Electrical Technical Univ., St Petersburg, Russia, Sept 1999, LNCS 1662 Springer-Verlag, pp. 207–216.
Dalton: Analysis of an Associative Array Parallel Logic Simulator; International Workshops on Parallel Processing (28th International Conference on Parallel Processing, ICPP'99), Wakamatsu, Japan, September 1999, IEEE Computer Press.
Dalton: Avoiding Conventional Overheads in Parallel Logic Simulation; A New Architecture; Proc Int'l Conf on High Performance Computing ACM/IEEE, Calcutta, India, December 1999, LNCS Springer Verlag Vol 1745, ISBN 978-3-540-66907-4, pp. 364–370.
Dalton, Bessler et al: APPLES: A Full Gate-timing FPGA-Based Hardware Simulator; 13th Int'l Conf on Field Programmable Logic and Applications, FPL 2003, Lisbon, Portugal, Sept 2003, LNCS 2778 Springer Verlag, pp. 1162–1165.
Dalton, McCarthy, Vadher, Polaschegg, Steger: Power Calculation with the Parallel APPLES Simulator; Proceedings of the Workshop on Mobile Computing (TCMC 2003), Graz, Austria, March 2003.
Maili, Dalton, Steger: A Generic Timing Mechanism for Using the APPLES Gate-level Simulator in a Mixed-level Simulation Environment; 14th Int'l Workshop on Power and Timing Modelling, Optimisation and Simulation, Patmos, Greece, Sept 2004, LNCS Springer-Verlag Vol 3254, ISBN 978-3-540-23095-3, pp. 799–808.
Polaschegg, Steger, Dalton, Vadher: A Generic Simulation Framework for Multiprocessor Architectures; FDL’04 (Forum on Specification and Design Languages), Lille, Sept 2004, ECSI (European Electronic Chips and Systems Design Initiative).
Ulrich Neffe, Klaus Rothbart, Christian Steger, Reinhold Weiss, E. Rieger, and A. Mühlbacher. A Flexible and Accurate Energy Model of an Instruction-Set Simulator for Secure Software Design. Proceedings of the Fourteenth International Workshop on Power and Timing Modeling, Optimization and Synthesis, Santorini, Greece, September 2004.
Maili, Steger, Weiss, Dalton: An architecture to enable on-chip cosimulation of IP-models with the APPLES gate-level accelerator; Proceedings of the Workshop on Mobile Computing (TCMC 2005), Graz, Austria, March 2005.
Neffe, Rothbart, Steger, Weiss, Rieger, Mühlberger, "An Abstraction and Optimization Approach Using HW/SW Codesign Techniques to get Power Aware Smart Card Solutions", The 2005 International Conference on Embedded Systems and Applications (ESA'05), Las Vegas, USA, 2005.
Kajtazovic, Steger, and Pistauer: A HDL-Independent Modeling Methodology for Heterogeneous System Designs. In Proceedings of the 2005 IEEE International Behavioral Modeling and Simulation Workshop BMAS 2005, San Jose, California, USA, September, 2005.
Maili, Steger, Weiss, Dalton: Combining a gate-level accelerator with an on-chip processor to reduce the communication bottleneck; Proceedings of the Austrochip05, Vienna, Austria, October 2005, pp. 199–206.
Polaschegg, Steger, Dalton, Vadher: Parallel Simulation with a Generic Simulation Framework Featuring Loose Coupling; Proceedings of the 2005 International Conference on Parallel Processing Workshops, Oslo, Norway, June 2005, IEEE Computer Society, ISBN 0-7695-2381-1, pp. 251–257.
Maili, Steger, Weiss, Dalton, Quigley: Reducing the Communication Bottleneck via On-chip Cosimulation of Gate-Level HDL and C-models on a Hardware Accelerator; 2005 IEEE Computer
Polaschegg, Steger, Dalton, Vadher. Using Hierarchical Structures in Generic Simulation Framework for Multiprocessor Architectures; Proceedings of the 6th WSEAS International Conference on Software Engineering, Parallel and Distributed Systems (SEPADS05), Salzburg, Austria, February 2005, Volume 2, pp. 209–214.
Maili, Steger, Weiss, Dalton: An Architecture to Enable On-Chip Cosimulation of IP-models with the APPLES Gate Simulator; (TCMC05) Telecommunications and Mobile Computing Graz Series 2005.
Maili, Steger, Weiss, Dalton, Quigley: Reducing the Communication Bottleneck via On-chip Cosimulation of Gate-Level HDL and C-models on a Hardware Accelerator; 2005 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2005), Tampa, Florida, USA.
Griffiths, Jeffery: The Analysis and Design of a Cache System and Data Pre-Fetching Algorithm for a Gate-level Simulator: Ph.D Thesis, University College Dublin, Ireland, 2006.
McCarthy, Andrew: Design and Implementation of a Parallel System of APPLES Processors. Ph.D Thesis, University College Dublin, Ireland, 2006.
Grumer, Steger, Wendt, Muehlberger, Neffe, Horizontal and Vertical HW/SW Codesign Flows for Power Aware Smart Card Designs, International Journal of Embedded Systems (IJES) 2006, Special Issue on Power-aware Computing Systems, Volume 2, Issue 3, 2006.
Polaschegg, Steger, Dalton, McCarthy: Performance Evaluation of a Parallel Processing System and Development using Parallel Simulation; Proceedings of the 2006 International Symposium on Performance Evaluation of Computer and Telecommunication Systems (SPECTS'06), Calgary, Alberta, Canada, July/August 2006, Simulation Series Volume 38, Number 3, ISBN 1-565555-308-X, pp. 232–246.
Janek, Trummer, Steger, Weiss, Preishuber-Pfluegl, Pistauer: Lifecycle Extension of Long Range UHF RFID Tags based on Energy Harvesting: The First International EURASIP Workshop on RFID Technology, RFID2007, Vienna, Austria.
Quigley, Dalton, Steger: Accelerating Assertion Based Verification with FPGA Co-processing: IEEE 8th Workshop on RTL and High Level Testing, WRTLT'07, October 12-13, 2007, Beijing, China.
Grumer, Wendt, Steger, Muehlberger, Neffe:" Automated Instruction Set Characterization and Power Profile Driven Software Optimization for Mobile Devices", in Special issue of Journal of Embedded Computing (JEC), 2008.
Leeney, Hugo: Simulation Based Power Analysis with APPLES. Ph.D Thesis, University College Dublin, Ireland, 2008.
Kirchsteiger, Grinschgl, Trummer, Steger, Weiss, Pistauer: .Automatic Test Generation From Semi-formal Specifications for Functional Verification of System-on-Chip Designs; 2nd Annual IEEE Systems Conference, 2008 7-10 April 2008.
Kirchsteiger, Trummer, Steger, Weiss, Pistauer: Specification-based Verification of Embedded Systems by Automated Testcase Generation; IFIP Working Conference on Distributed and Parallel Embedded Systems (DIPES'08), September 7-10, 2008, Milano, Italy.
Kirchsteiger, Schweitzer, Trummer, Steger, Weiss, Pistauer: A Software Performance Simulation Methodology for Rapid System Architecture Exploration; The 15th IEEE International Conference on Electronics, Circuits and Systems (ICECS'08),31st August - 3rd September 2008, Malta.
Books
Kajtazovic, Steger, Schuhai, and Pistauer: Automatic generation of a verification platform for heterogeneous system designs. In Advances in Design and Specification Languages for SoCs - Selected Contributions from FDL'05, Vachoux, Alain (Ed.), Kluwer Academic Publishers Boston/Dordrecht/London, 2006.