Now a member of the Synopsys System-Level Catalyst Program!
Neosera Systems is pleased to announce it has joined the Synopsys System-Level Catalyst Program.
Solutions for Low Power ESL to Gate-Level Design
Neosera is the leader in power solutions for system and software design. From IC design to embedded electronic devices, as well as mobile devices and applications, Neosera provides solutions which measure and optimize power at each point of the development process.
Neosera ESL to Gate-level Power and Simulation Tool Technology
System to Gate-level Power Estimation and Analysis Tools:
- RHEiMS: Rapid Hierarchical Energy Investigation and Modeling System is a unique and innovative system-level power estimation tool compatible with any system-level simulation language. Rheims delivers power estimation 3 orders of magnitude faster but within 2% accuracy of gate-level power tools.
- RHEiMS-OPSL: RHEiMS-OPtimisation at System-Level is an extension to RHEiMS that determines the optimum system-level operating conditions (e.g. Frequency and voltage levels of each component) subject to various user-defined constraints.
- RHEiMS-PRTL: RHEiMS-Power at Register Transfer-Level is an extension to RHEiMS that integrates various RHEiMS power models into Verilog or VHDL delivering power 2 orders of magnitude faster but within 2% accuracy of gate-level power tools.
- ENiGMA: ENergy Investigation via Gate and Module Analysis is a hardware accelerator that provides rapid cycle-accurate power estimation at the gate-level. Dynamic and leakage power estimation is analysed on a cycle by cycle module and gate basis. It can be used, though not necessary with RHEiMS.
System to Gate-level Simulation Tools:
- RHEiMS-ISS: A stand-alone Instruction Set Simulator that can be integrated in System-level tools. The simulator takes into account compiler optimisations and the cache and pipeline structure of the target processor and delivers speed performance between 1 and 3 orders of magnitude faster existing simulators.
- APPLES: Associative Parallel Processor for Logic Event-driven Simulation is a cycle-accurate, hardware accelerated gate-level simulator. APPLES accelerates both the gate modeling and testbench in the logic simulation process. It can be used to accelerate the ENiGMA tool.
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